{"success":true,"data":{"company":{"name":"Avicena","domain":"avicena","role_match_capture":false},"jobs":[{"uuid":"6de2e853-6db2-47bb-9541-b96468096060","title":"ASIC Design Verification Engineer","content":"**Job Title**\n\nASIC Design Verification Engineer\n\n**Job description**\n\nAvicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team.  \nYou'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions.  \nThis position requires strong expertise in verification methodology and a commitment to quality.\n\n**Responsibilities**\n\n- **Testbench Development:** Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology).  \n- **Verification Planning:** Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals.  \n- **Test Case Creation:** Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models.  \n- **Functional Debugging:** Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes.  \n- **Coverage Closure:** Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality.  \n- **Regression Management:** Maintain and manage regression suites, optimizing simulation speed and efficiency.  \n- **Formal Verification:** Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines.  \n- **Scripting and Automation:** Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency.\n\n**Qualifications**\n\n*Required:*\n\n- **Education:** Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.  \n- **Experience:** 3+ years of professional experience in ASIC\/SoC design verification.  \n- **UVM Expertise:** Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.  \n- **Verification Languages:** Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.  \n- **Tool Proficiency:** Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).  \n- **Coverage Driven Methodology:** Solid understanding of constrained-random verification and functional\/code coverage analysis.  \n- **Debugging Skills:** Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments.\n\n*Preferred (Nice to Have):*\n\n- **Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe.**  \n- **Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques.**  \n- **Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold).**  \n- **Familiarity with low-power verification techniques.**  \n- **Experience with hardware description languages (HDL) like Verilog\/SystemVerilog for basic design understanding.**  \n- **Exposure to physical layer (PHY) or mixed-signal verification concepts.**","url":"https:\/\/ats.rippling.com\/general\/jobs\/f9df189f-0608-46ef-8c26-4e7adde76215","created_at":"2025-10-08T21:47:37.000000Z","department":"ASIC Development Engineering","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nASIC Design Verification Engineer\n\n**Job description**\n\nAvicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team.  \nYou'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions.  \nThis position requires strong expertise in verification methodology and a commitment to quality.\n\n**Responsibilities**\n\n- **Testbench Development:** Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology).  \n- **Verification Planning:** Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals.  \n- **Test Case Creation:** Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models.  \n- **Functional Debugging:** Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes.  \n- **Coverage Closure:** Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality.  \n- **Regression Management:** Maintain and manage regression suites, optimizing simulation speed and efficiency.  \n- **Formal Verification:** Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines.  \n- **Scripting and Automation:** Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency.\n\n**Qualifications**\n\n*Required:*\n\n- **Education:** Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.  \n- **Experience:** 3+ years of professional experience in ASIC\/SoC design verification.  \n- **UVM Expertise:** Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.  \n- **Verification Languages:** Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.  \n- **Tool Proficiency:** Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).  \n- **Coverage Driven Methodology:** Solid understanding of constrained-random verification and functional\/code coverage analysis.  \n- **Debugging Skills:** Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments.\n\n*Preferred (Nice to Have):*\n\n- **Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe.**  \n- **Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques.**  \n- **Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold).**  \n- **Familiarity with low-power verification techniques.**  \n- **Experience with hardware description languages (HDL) like Verilog\/SystemVerilog for basic design understanding.**  \n- **Exposure to physical layer (PHY) or mixed-signal verification concepts.**","categories":["Engineering"],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"e5e554e6-c2c3-437e-b03c-db5b18083a69","title":"Software Intern for system integration","content":"**Job Title**\n\nSoftware Intern for system integration 2026\n\n**Job description**\n\n**About the Role**\n\n- As a Software Engineering Intern with hardware experience at Avicena, you will gain hands-on experience in both hardware validation and software development.\n- You will work closely with engineers on a variety of tasks including testing hardware components, developing software tools, and creating intuitive graphical user interfaces (GUIs) for embedded systems.\n- This internship will provide valuable exposure to industry best practices in both hardware and software, and give you the chance to develop solutions that improve the functionality of our products.\n\n**Responsibilities**\n\n**Hardware Validation**\n\n- Assist in validating and troubleshooting hardware components such as PCBs and microcontrollers.\n\n**Software Development**\n\n- Develop software tools and scripts in Python for automating hardware validation, data collection, and analysis.\n- Write clean, maintainable, and efficient Python code to interact with embedded systems and devices.\n\n**Qualifications**\n\n**Education**\n\n- Currently pursuing a degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n\n**Technical Skills**\n\n**Hardware Experience**\n\n- Hands-on experience with standard electronics tools like multimeters, oscilloscopes, and power supplies.\n- Solid understanding of basic electronics concepts, including circuit design and signal analysis.\n\n**Software Development**\n\n- Proficient in Python programming for automation, data collection, and software testing.\n- Experience with GUI development using PyQt6 or similar frameworks (Tkinter, Kivy).\n\n**Communication Protocols**\n\n- Familiarity with communication protocols such as SPI, I2C, UART, and related interfaces.\n\n**Version Control**\n\n- Comfortable using Git for version control, including branching, merging, and pull requests.\n\n**Other Skills**\n\n- Strong problem-solving skills and ability to troubleshoot both hardware and software issues.\n- Ability to work independently and as part of a team in a fast-paced environment.\n- Strong communication skills, both written and verbal.\n- Attention to detail and strong organizational skills.\n\n**Preferred Qualifications (Not Required)**\n\n- Experience with embedded systems or microcontroller programming (e.g., Arduino, Raspberry Pi).\n- Knowledge of Linux-based operating systems and command-line tools.\n- Familiarity with other programming languages such as C\/C++.","url":"https:\/\/ats.rippling.com\/general\/jobs\/36a05835-ab48-487f-8806-48404b8f0d09","created_at":"2026-04-02T23:19:25.000000Z","department":"Software & GUI","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nSoftware Intern for system integration 2026\n\n**Job description**\n\n**About the Role**\n\n- As a Software Engineering Intern with hardware experience at Avicena, you will gain hands-on experience in both hardware validation and software development.\n- You will work closely with engineers on a variety of tasks including testing hardware components, developing software tools, and creating intuitive graphical user interfaces (GUIs) for embedded systems.\n- This internship will provide valuable exposure to industry best practices in both hardware and software, and give you the chance to develop solutions that improve the functionality of our products.\n\n**Responsibilities**\n\n**Hardware Validation**\n\n- Assist in validating and troubleshooting hardware components such as PCBs and microcontrollers.\n\n**Software Development**\n\n- Develop software tools and scripts in Python for automating hardware validation, data collection, and analysis.\n- Write clean, maintainable, and efficient Python code to interact with embedded systems and devices.\n\n**Qualifications**\n\n**Education**\n\n- Currently pursuing a degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.\n\n**Technical Skills**\n\n**Hardware Experience**\n\n- Hands-on experience with standard electronics tools like multimeters, oscilloscopes, and power supplies.\n- Solid understanding of basic electronics concepts, including circuit design and signal analysis.\n\n**Software Development**\n\n- Proficient in Python programming for automation, data collection, and software testing.\n- Experience with GUI development using PyQt6 or similar frameworks (Tkinter, Kivy).\n\n**Communication Protocols**\n\n- Familiarity with communication protocols such as SPI, I2C, UART, and related interfaces.\n\n**Version Control**\n\n- Comfortable using Git for version control, including branching, merging, and pull requests.\n\n**Other Skills**\n\n- Strong problem-solving skills and ability to troubleshoot both hardware and software issues.\n- Ability to work independently and as part of a team in a fast-paced environment.\n- Strong communication skills, both written and verbal.\n- Attention to detail and strong organizational skills.\n\n**Preferred Qualifications (Not Required)**\n\n- Experience with embedded systems or microcontroller programming (e.g., Arduino, Raspberry Pi).\n- Knowledge of Linux-based operating systems and command-line tools.\n- Familiarity with other programming languages such as C\/C++.","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"d800be68-b086-4d99-bbfa-10056b5ea7e5","title":"Support Desk Specialist","content":"**Job Title**\n\nSupport Desk Specialist\n\n**job description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\n- We are seeking a responsible and technically skilled Helpdesk Support Technician to join our team. The ideal candidate will have a passion for troubleshooting, a solid understanding of Windows 11, Microsoft 365, and a working knowledge of TCP\/IP. You will be responsible for providing application support, assisting users with technical issues, managing hardware support, and ensuring tasks are handled in a timely and efficient manner.\n- This role also requires providing after-hours support and maintaining high levels of customer satisfaction through exceptional service delivery.\n\n**Responsibilities**\n\n- Provide remote support to end-users via phone, email, or chat, ensuring timely and effective resolution of technical issues.\n- Troubleshoot and resolve hardware issues, including desktops, laptops, printers, network multifunction copiers, and peripheral devices.\n- Provide support for Windows 11, and Microsoft 365 environments, troubleshooting software and system-related issues.\n- Microsoft Outlook, Word, PowerPoint, SharePoint, and OneDrive\n- Offer application support for various software programs and internal tools.\n- Utilize ticketing systems to log, track, and manage technical support requests.\n- Maintain a thorough understanding of TCP\/IP networking, helping to diagnose and resolve connectivity issues.\n- Install applications, troubleshoot user issues,\n- Collaborate with team members to address complex issues and escalate as necessary.\n- Provide after-hours support or holiday support as required and participate in the on-call to support critical issues.\n- Demonstrate a willingness to learn new technologies and processes, improving technical expertise and service delivery.\n\n**Qualifications**\n\n- Minimum of 2 years of experience in helpdesk and user support roles.\n- Strong technical knowledge of Windows 11, and Microsoft 365.\n- Experience providing hardware support for desktops, laptops, printers, network multifunction copiers, and peripherals.\n- Working knowledge of TCP\/IP and general networking principles.\n- Experience with DNS, DHCP, PING, Drive Mapping, Network connections.\n- Proven ability to troubleshoot technical issues and provide timely resolutions.\n- Good communication skills, both verbal and written, with a focus on clear and concise customer interactions.\n- Strong problem-solving skills and attention to detail.\n- Ability to work independently and manage multiple tasks effectively in a fast-paced environment.\n- Familiarity with SSO and MFA.\n\n**Preferred Qualifications**\n\n- Experience with remote desktop tools and remote support software.\n- Basic knowledge of Windows servers management.\n- Experience with Active Directory is preferred.\n- Degree in Computer Science or Information Technology is preferred.","url":"https:\/\/ats.rippling.com\/general\/jobs\/85aa94ad-a796-4265-bd33-e5ea6a016b7c","created_at":"2026-04-09T18:16:27.000000Z","department":"G & A","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nSupport Desk Specialist\n\n**job description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\n- We are seeking a responsible and technically skilled Helpdesk Support Technician to join our team. The ideal candidate will have a passion for troubleshooting, a solid understanding of Windows 11, Microsoft 365, and a working knowledge of TCP\/IP. You will be responsible for providing application support, assisting users with technical issues, managing hardware support, and ensuring tasks are handled in a timely and efficient manner.\n- This role also requires providing after-hours support and maintaining high levels of customer satisfaction through exceptional service delivery.\n\n**Responsibilities**\n\n- Provide remote support to end-users via phone, email, or chat, ensuring timely and effective resolution of technical issues.\n- Troubleshoot and resolve hardware issues, including desktops, laptops, printers, network multifunction copiers, and peripheral devices.\n- Provide support for Windows 11, and Microsoft 365 environments, troubleshooting software and system-related issues.\n- Microsoft Outlook, Word, PowerPoint, SharePoint, and OneDrive\n- Offer application support for various software programs and internal tools.\n- Utilize ticketing systems to log, track, and manage technical support requests.\n- Maintain a thorough understanding of TCP\/IP networking, helping to diagnose and resolve connectivity issues.\n- Install applications, troubleshoot user issues,\n- Collaborate with team members to address complex issues and escalate as necessary.\n- Provide after-hours support or holiday support as required and participate in the on-call to support critical issues.\n- Demonstrate a willingness to learn new technologies and processes, improving technical expertise and service delivery.\n\n**Qualifications**\n\n- Minimum of 2 years of experience in helpdesk and user support roles.\n- Strong technical knowledge of Windows 11, and Microsoft 365.\n- Experience providing hardware support for desktops, laptops, printers, network multifunction copiers, and peripherals.\n- Working knowledge of TCP\/IP and general networking principles.\n- Experience with DNS, DHCP, PING, Drive Mapping, Network connections.\n- Proven ability to troubleshoot technical issues and provide timely resolutions.\n- Good communication skills, both verbal and written, with a focus on clear and concise customer interactions.\n- Strong problem-solving skills and attention to detail.\n- Ability to work independently and manage multiple tasks effectively in a fast-paced environment.\n- Familiarity with SSO and MFA.\n\n**Preferred Qualifications**\n\n- Experience with remote desktop tools and remote support software.\n- Basic knowledge of Windows servers management.\n- Experience with Active Directory is preferred.\n- Degree in Computer Science or Information Technology is preferred.","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":{"min":60000,"max":75000,"currency":"USD","period":"YEARLY"}},{"uuid":"947707a7-4faa-423a-bd55-993357a1d398","title":"TX\/RX subcomponent testing engineer","content":"**Job Title**\n\nTX\/RX subcomponent testing engineer\n\n**Job Description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**Responsibilities**\n\n- Characterization of subcomponents of optical transmitters, optical receivers used in parallel opto-electronic interfaces (Light emitting diodes (LEDs) and Photodetectors (PDs))\n- Work with the epitaxial development group to characterize the bandgap structure of LEDs, modulation speed, efficiency using various methods (spectroscopy, S21 measurement, SIMS, FIB, SEM, etc..)\n- Test photo detectors and extract the relevant parameters and provide feedback for the PD developers.\n- Maintain and improve opto-electronic test systems for full characterization of optical sub-components and modules.\n- Run link DOEs for sub-component development.\n\n**Qualifications**\n\n- MS or PhD in electrical engineering or physics with 2+ years of experience\n- Understanding of solid-state physics and physical principles behind LEDs PDs design and critical parameters of the transceiver system design based on LEDs and PDs.\n- Experience with LED\/PD characterization\n- Understanding of Optics\n\n**Preferred Qualifications**\n\n- Being able to execute DOEs, targeted to improve the performance of sub-components. Provide clear\/ concise data summary and conclusions\n- Strong verbal and written communication skills\n- Working knowledge of high-speed test instruments such as VNAs, sampling and real time oscilloscopes and spectrum analyzers, optical spectrometers\n- Hands-on lab experience especially with probed\/free space coupled (using stages) optical systems","url":"https:\/\/ats.rippling.com\/general\/jobs\/baacff6c-c5dd-41d3-ba3b-ba21ef035b08","created_at":"2026-04-10T14:23:12.000000Z","department":"Product Engineering","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nTX\/RX subcomponent testing engineer\n\n**Job Description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**Responsibilities**\n\n- Characterization of subcomponents of optical transmitters, optical receivers used in parallel opto-electronic interfaces (Light emitting diodes (LEDs) and Photodetectors (PDs))\n- Work with the epitaxial development group to characterize the bandgap structure of LEDs, modulation speed, efficiency using various methods (spectroscopy, S21 measurement, SIMS, FIB, SEM, etc..)\n- Test photo detectors and extract the relevant parameters and provide feedback for the PD developers.\n- Maintain and improve opto-electronic test systems for full characterization of optical sub-components and modules.\n- Run link DOEs for sub-component development.\n\n**Qualifications**\n\n- MS or PhD in electrical engineering or physics with 2+ years of experience\n- Understanding of solid-state physics and physical principles behind LEDs PDs design and critical parameters of the transceiver system design based on LEDs and PDs.\n- Experience with LED\/PD characterization\n- Understanding of Optics\n\n**Preferred Qualifications**\n\n- Being able to execute DOEs, targeted to improve the performance of sub-components. Provide clear\/ concise data summary and conclusions\n- Strong verbal and written communication skills\n- Working knowledge of high-speed test instruments such as VNAs, sampling and real time oscilloscopes and spectrum analyzers, optical spectrometers\n- Hands-on lab experience especially with probed\/free space coupled (using stages) optical systems","categories":["R&D"],"employment_type":"FULL_TIME","experience_level":null,"workplace_type":"Onsite","salary":null},{"uuid":"b5a79b93-7bc3-4535-beb7-5031c4a5059f","title":"Advanced Packaging \u2013 Process Technician","content":"**Job Title**\n\nAdvanced Packaging \u2013 Process Technician\n\n**Job Description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\n- As a process technician in our clean room, your responsibilities may include being responsible for performing technical tests and experiments for engineering in the wafer fabrication area of semiconductor manufacturers.\n- Process technicians also test new products and provide technical assistance to process development and engineering personnel.\n- This technician will be a valuable part of the team, interfacing and communicating with engineering and manufacturing groups across the fab to ensure all issues are solved appropriately and efficiently.\n- Additionally, you will provide process and product support to the organization and address production concerns and disposition of production material.\n\n**Responsibilities**\n\n- Ability to identify, multi-task, and resolve multiple priority issues quickly and efficiently to improve overall fab performance.\n- Ability to learn and understand process flow quickly and support the engineering organization as needed.\n- Exceptional attention to detail\n- Strong collaborative skills in team environment\n- Excellent verbal and written communications skills.\n- Perform other designated tasks as assigned by management.\n- Comfortable in a clean room environment.\n- Proficient with MS Office, Word and Excel\n\n**Qualifications**\n\n- AA degree or 4 years of experience in a cleanroom fab is preferred.\n- Experience with Flip Chip Bonding, flux dispense, underfill dispense, profilometry, optical microscope inspection and related operations.\n- Familiar with probe station and experience of electrical test is a plus.\n- Preferred: Experience with operating lasers and its related safety protocols.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6705c69543999182fe9e7873\/overview","created_at":"2026-04-11T02:30:15.000000Z","department":"FAB & Manufacturing","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nAdvanced Packaging \u2013 Process Technician\n\n**Job Description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\n- As a process technician in our clean room, your responsibilities may include being responsible for performing technical tests and experiments for engineering in the wafer fabrication area of semiconductor manufacturers.\n- Process technicians also test new products and provide technical assistance to process development and engineering personnel.\n- This technician will be a valuable part of the team, interfacing and communicating with engineering and manufacturing groups across the fab to ensure all issues are solved appropriately and efficiently.\n- Additionally, you will provide process and product support to the organization and address production concerns and disposition of production material.\n\n**Responsibilities**\n\n- Ability to identify, multi-task, and resolve multiple priority issues quickly and efficiently to improve overall fab performance.\n- Ability to learn and understand process flow quickly and support the engineering organization as needed.\n- Exceptional attention to detail\n- Strong collaborative skills in team environment\n- Excellent verbal and written communications skills.\n- Perform other designated tasks as assigned by management.\n- Comfortable in a clean room environment.\n- Proficient with MS Office, Word and Excel\n\n**Qualifications**\n\n- AA degree or 4 years of experience in a cleanroom fab is preferred.\n- Experience with Flip Chip Bonding, flux dispense, underfill dispense, profilometry, optical microscope inspection and related operations.\n- Familiar with probe station and experience of electrical test is a plus.\n- Preferred: Experience with operating lasers and its related safety protocols.","categories":["Engineering"],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"e94bc66b-302e-44e5-8416-ae4b7a037c40","title":"MOCVD Equipment Engineer","content":"**Job Title**\n\nMOCVD Equipment Engineer\n\n**About the role**\n\n- We are now expanding our device fabrication cleanroom facility for process development and ultra-low volume production. The individual in this role will play a key role in creating the world-class capabilities necessary to produce these unique devices. This role requires a highly diverse skill set with strong problem-solving skills. In this position, you will support all EPI reactor tool and corresponding support equipment- this includes but not limited to \u2013 reactor scrubber, Hydrogen source (all forms) process metrology tools. The entire preventative maintenance and optimization functions of all EPI wafer fabrication process equipment of our micro LED devices.\n\n**Responsibilities**\n\n- Own equipment uptime performance, including installation, acceptance, qualification, and lifecycle management of EPI reactors and all associated support systems.\n- Conducts and assists with hands-on preventative maintenance, unplanned repairs and optimization tasks of all EPI equipment and supporting ancillary equipment\n- Develop and implement robust preventative maintenance plans in accordance with OEM recommendations for EPI tool and support equipment\n- Coordinates and acts as point of contact with OEM equipment manufacturers with all warranty, retrofit and repair activities\n- Develops and maintains a comprehensive database of critical spare parts and consumables to minimize downtime\n- Reviews and assist in maintaining compressed process gas delivery systems and when required, assist in performing routine bottle changes\n- Evaluates and implements plans to improve equipment uptime and performance\n- Develop and manage off-site parts refurbishment and cleaning programs\n- Partner with Process Engineering to identify equipment-related yield and process stability improvements and implement corrective actions.\n- Support and participate in Environmental, Safety and Health programs\n- Active member of the site emergency response team (ERT)\n\n**Qualifications**\n\n- 10+ years of hands-on experience supporting MOCVD reactors, with direct experience on Aixtron\u00b7 G3\/G4\/G5 or Veeco\/Emcore platforms\n- arsenide\u2019s, phosphides, or nitrides strongly preferred Hands-on maintenance and repair experience in all relevant EPI reactor and direct reactor support tools. Hands-on maintenance and repair experience in all relevant EPI reactor and reactor support tools including metrology, NH3 (purifier) and Hydrogen supply (all forms of supply gases)\n- The ability to wear a respirator and self-contained breathing apparatus (SCBA)\n- Comfortable working in Clean Room environment; experience with Clean Room hygiene protocols\n- Comfortable working with hazardous chemicals; experience with hazmat handling protocols\n- Excellent oral and written communications skills, self-motivated, ability to work in team environment\n- High degree of comfort with flexible, agile small company environment\n\n**Preferred Qualifications**\n\n- In-depth understanding of electronics, vacuum technologies (i.e. Helium leak checking, dry vac pump rebuild) and metrology tools\n- Cross-functional experience in both research and production environments\n- Experience using relevant software programs, including MS office, Fab MES, SPC, and others","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/69d0373055e0b9345756faa8\/overview","created_at":"2026-06-11T16:41:51.000000Z","department":"Equipment Maintenance","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nMOCVD Equipment Engineer\n\n**About the role**\n\n- We are now expanding our device fabrication cleanroom facility for process development and ultra-low volume production. The individual in this role will play a key role in creating the world-class capabilities necessary to produce these unique devices. This role requires a highly diverse skill set with strong problem-solving skills. In this position, you will support all EPI reactor tool and corresponding support equipment- this includes but not limited to \u2013 reactor scrubber, Hydrogen source (all forms) process metrology tools. The entire preventative maintenance and optimization functions of all EPI wafer fabrication process equipment of our micro LED devices.\n\n**Responsibilities**\n\n- Own equipment uptime performance, including installation, acceptance, qualification, and lifecycle management of EPI reactors and all associated support systems.\n- Conducts and assists with hands-on preventative maintenance, unplanned repairs and optimization tasks of all EPI equipment and supporting ancillary equipment\n- Develop and implement robust preventative maintenance plans in accordance with OEM recommendations for EPI tool and support equipment\n- Coordinates and acts as point of contact with OEM equipment manufacturers with all warranty, retrofit and repair activities\n- Develops and maintains a comprehensive database of critical spare parts and consumables to minimize downtime\n- Reviews and assist in maintaining compressed process gas delivery systems and when required, assist in performing routine bottle changes\n- Evaluates and implements plans to improve equipment uptime and performance\n- Develop and manage off-site parts refurbishment and cleaning programs\n- Partner with Process Engineering to identify equipment-related yield and process stability improvements and implement corrective actions.\n- Support and participate in Environmental, Safety and Health programs\n- Active member of the site emergency response team (ERT)\n\n**Qualifications**\n\n- 10+ years of hands-on experience supporting MOCVD reactors, with direct experience on Aixtron\u00b7 G3\/G4\/G5 or Veeco\/Emcore platforms\n- arsenide\u2019s, phosphides, or nitrides strongly preferred Hands-on maintenance and repair experience in all relevant EPI reactor and direct reactor support tools. Hands-on maintenance and repair experience in all relevant EPI reactor and reactor support tools including metrology, NH3 (purifier) and Hydrogen supply (all forms of supply gases)\n- The ability to wear a respirator and self-contained breathing apparatus (SCBA)\n- Comfortable working in Clean Room environment; experience with Clean Room hygiene protocols\n- Comfortable working with hazardous chemicals; experience with hazmat handling protocols\n- Excellent oral and written communications skills, self-motivated, ability to work in team environment\n- High degree of comfort with flexible, agile small company environment\n\n**Preferred Qualifications**\n\n- In-depth understanding of electronics, vacuum technologies (i.e. Helium leak checking, dry vac pump rebuild) and metrology tools\n- Cross-functional experience in both research and production environments\n- Experience using relevant software programs, including MS office, Fab MES, SPC, and others","categories":["Engineering"],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"036cc22a-803c-41de-b6f7-22cd67dedb89","title":"Director, PD development and integration","content":"**Job Title**\n\nDirector, PD development and integration\n\n**About the role**\n\n- We are seeking a highly skilled team member to lead the development and manufacturing transfer of high-speed silicon photodetectors (PDs) optimized for microLED-based multi-terabit-per-second communications.  \n- This role focuses on managing critical partnerships and processes to enable the successful development and transfer of photodetectors into high-volume manufacturing working with leading semiconductor fabrication partners.  \n- This position is based in Sunnyvale, California.  \n- This position starts with a single hire with a plan to grow the team as the company and product develops.  \n- This is an ideal opportunity for someone looking to develop into a senior engineering management position.  \n\n**Responsibilities**\n\n- **New PD Design Development:** Lead the development of innovative PD designs optimized for our applications. Work with internal and external resources to design and simulate PD performance. Work with internal resources to characterize PDs.  \n- **Foundry Partnership Management:** Lead and manage the foundry partnership, including the transfer of new photodetector designs and oversee any necessary process modifications. Ensure alignment between Avicena\u2019s technical and business requirements and the foundry partner\u2019s capabilities.  \n- **Wafer Testing Management:** Oversee the development and implementation of wafer testing strategies, including identifying and managing external vendors for wafer-level testing. Leverage expertise to define and validate test methodologies.  \n- **Final Test Development:** Collaborate with vendors to set up and manage final test processes, ensuring robust performance validation of packaged devices.  \n- **Qualification:** Work with a multi-disciplinary team to establish qualification of Avicena\u2019s manufacturing flows and ultimate qualification to industry standards.  \n\n**Qualifications**\n\n- **Educational Background:**  \n  - BS, MS, or PhD in Materials Science and Engineering, Electrical Engineering, or Applied Physics.  \n- **Industry Experience:**  \n  - Proven experience managing foundry partnerships or foundry processes.  \n  - Deep understanding of semiconductor device physics and characterization techniques (e.g., SIMS, XRD, SEM, TEM).  \n  - Familiarity with semiconductor wafer fabrication processes, including photolithography, thin-film deposition, and etching.  \n  - Experience with packaging technologies, including hybrid bonding and wafer stacking is a plus.  \n  - Ability to manage outsourcing to high volume manufacturing partners.  \n- **Testing Expertise:**  \n  - Ability to oversee high-speed optoelectronics testing, including wafer-level and final test processes.  \n- **Project Management Skills:**  \n  - Excellent interpersonal and communication skills to collaborate with internal teams, manage external vendors, and present complex technical findings.  \n  - Ability to manage timelines, overcome technical challenges, and drive solutions in a dynamic work environment.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/69dd357073da8c224612440a\/overview","created_at":"2026-06-13T02:11:14.000000Z","department":"PD","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nDirector, PD development and integration\n\n**About the role**\n\n- We are seeking a highly skilled team member to lead the development and manufacturing transfer of high-speed silicon photodetectors (PDs) optimized for microLED-based multi-terabit-per-second communications.  \n- This role focuses on managing critical partnerships and processes to enable the successful development and transfer of photodetectors into high-volume manufacturing working with leading semiconductor fabrication partners.  \n- This position is based in Sunnyvale, California.  \n- This position starts with a single hire with a plan to grow the team as the company and product develops.  \n- This is an ideal opportunity for someone looking to develop into a senior engineering management position.  \n\n**Responsibilities**\n\n- **New PD Design Development:** Lead the development of innovative PD designs optimized for our applications. Work with internal and external resources to design and simulate PD performance. Work with internal resources to characterize PDs.  \n- **Foundry Partnership Management:** Lead and manage the foundry partnership, including the transfer of new photodetector designs and oversee any necessary process modifications. Ensure alignment between Avicena\u2019s technical and business requirements and the foundry partner\u2019s capabilities.  \n- **Wafer Testing Management:** Oversee the development and implementation of wafer testing strategies, including identifying and managing external vendors for wafer-level testing. Leverage expertise to define and validate test methodologies.  \n- **Final Test Development:** Collaborate with vendors to set up and manage final test processes, ensuring robust performance validation of packaged devices.  \n- **Qualification:** Work with a multi-disciplinary team to establish qualification of Avicena\u2019s manufacturing flows and ultimate qualification to industry standards.  \n\n**Qualifications**\n\n- **Educational Background:**  \n  - BS, MS, or PhD in Materials Science and Engineering, Electrical Engineering, or Applied Physics.  \n- **Industry Experience:**  \n  - Proven experience managing foundry partnerships or foundry processes.  \n  - Deep understanding of semiconductor device physics and characterization techniques (e.g., SIMS, XRD, SEM, TEM).  \n  - Familiarity with semiconductor wafer fabrication processes, including photolithography, thin-film deposition, and etching.  \n  - Experience with packaging technologies, including hybrid bonding and wafer stacking is a plus.  \n  - Ability to manage outsourcing to high volume manufacturing partners.  \n- **Testing Expertise:**  \n  - Ability to oversee high-speed optoelectronics testing, including wafer-level and final test processes.  \n- **Project Management Skills:**  \n  - Excellent interpersonal and communication skills to collaborate with internal teams, manage external vendors, and present complex technical findings.  \n  - Ability to manage timelines, overcome technical challenges, and drive solutions in a dynamic work environment.","categories":["Engineering"],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"3bf37c28-c5fc-4d1f-8adb-80c9936a9364","title":"System test and characterization engineer","content":"**Job Title**\n\nSystem test and characterization engineer\n\n**Responsibilities**\n\n- Lead a team of engineers to characterize optical transmitters, optical receivers and link performance of highly parallel opto-electronic interfaces.\n- Develop and maintain optical transmission system testing bed for full characterization of optical components and modules as well as system performance measurements.\n- Define and run link DOEs using uLED on ASIC transmitters, fiber bundle as transmission and PD on ASIC as receivers.\n- Characterize various aspects of both existing and potential future optical components such as evaluating signal-to-noise ratio (SNR), receiver sensitivity, bit-error-rate (BER), crosstalk, power consumptions and link budget of the transmission system\n- Work with PCBA design engineers to design, fabricate and bring up test boards. Experience in schematic capture, circuit simulation and PCB design guidance\n\n**Qualifications**\n\n- MS or PhD in electrical engineering or physics with 3+ years of experience\n- Expertise with optical transceiver circuits such as Trans-impedance Amplifier (TIA), laser\/led drivers and photodetectors\n- Familiarity with datacenter class optical module designs for Quad Small Form-factor Pluggable Octal Small Form Factor Pluggable (QSFP)\/(OSFP) form factor pluggable modules or emerging Near-Packaged Optics (NPO) or Co-Packaged Optics (CPO) approaches.\n- Experience with optical transceiver test methodologies\n- Familiarity with industry standards including IEEE Ethernet standards, OIF standards and MSAs\n\n**Preferrred Qualifications**\n\n- Ability to work cross-functionally with ASIC, packaging and optical design teams and provide clear technical inputs\n- Strong verbal and written communication skills, and ability to articulate and engage with both technical and non-technical stakeholders at all levels\n- Ability to code scripts in python for validation and data analysis\n- Working knowledge of high-speed test instruments such as VNAs, sampling and real time oscilloscopes and spectrum analyzers\n- Hands-on lab experience especially with probed\/free space coupled (using stages) optical systems","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/69dd38d545aa4ca622805bf1\/overview","created_at":"2026-06-13T02:14:57.000000Z","department":"System Test & Characterization","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nSystem test and characterization engineer\n\n**Responsibilities**\n\n- Lead a team of engineers to characterize optical transmitters, optical receivers and link performance of highly parallel opto-electronic interfaces.\n- Develop and maintain optical transmission system testing bed for full characterization of optical components and modules as well as system performance measurements.\n- Define and run link DOEs using uLED on ASIC transmitters, fiber bundle as transmission and PD on ASIC as receivers.\n- Characterize various aspects of both existing and potential future optical components such as evaluating signal-to-noise ratio (SNR), receiver sensitivity, bit-error-rate (BER), crosstalk, power consumptions and link budget of the transmission system\n- Work with PCBA design engineers to design, fabricate and bring up test boards. Experience in schematic capture, circuit simulation and PCB design guidance\n\n**Qualifications**\n\n- MS or PhD in electrical engineering or physics with 3+ years of experience\n- Expertise with optical transceiver circuits such as Trans-impedance Amplifier (TIA), laser\/led drivers and photodetectors\n- Familiarity with datacenter class optical module designs for Quad Small Form-factor Pluggable Octal Small Form Factor Pluggable (QSFP)\/(OSFP) form factor pluggable modules or emerging Near-Packaged Optics (NPO) or Co-Packaged Optics (CPO) approaches.\n- Experience with optical transceiver test methodologies\n- Familiarity with industry standards including IEEE Ethernet standards, OIF standards and MSAs\n\n**Preferrred Qualifications**\n\n- Ability to work cross-functionally with ASIC, packaging and optical design teams and provide clear technical inputs\n- Strong verbal and written communication skills, and ability to articulate and engage with both technical and non-technical stakeholders at all levels\n- Ability to code scripts in python for validation and data analysis\n- Working knowledge of high-speed test instruments such as VNAs, sampling and real time oscilloscopes and spectrum analyzers\n- Hands-on lab experience especially with probed\/free space coupled (using stages) optical systems","categories":["Engineering"],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"a4e985bb-ec60-4420-9809-2e94373890e2","title":"Optical Fiber \u2013 Strategic Buyer\/Technologist","content":"**Job Title**\n\nOptical Fiber \u2013 Strategic Buyer\/Technologist\n\n**About the role**\n\n- Optical Fiber Strategic Buyer: Manage the sourcing, procurement, and supplier relationships for fiber optic cables. Key responsibilities include managing technical specifications, conducting supplier risk assessments, optimizing cost models, and ensuring supply continuity to meet project requirements.\n- Supplier Management: Identify, qualify, and manage key supplier relationships, establishing KPIs for quality, delivery, and cost performance.\n- Strategic Sourcing: Develop procurement strategies for optical components, including fiber optic cables.\n- Negotiation & Contracts: Negotiate pricing and terms & conditions.\n- Collaboration: Work with engineering, operations.\n- Fiber characterization: measure key parameters\n\n**Qualifications**\n\n- 5+ years of proven experience in strategic sourcing, ideally focusing on telecommunications, optical transport, or infrastructure.\n- Technical Knowledge: Understanding of optical fiber design, passive fiber connectivity, silicon photonics, and manufacturing processes.\n- Bachelors degree or higher in relevant technical field\n- Excellent teamwork and interpersonal\/communication skills within the company and with partners, customers, and consultants.\n- Good to have: Direct lab experience of fiber characterization and performance simulations.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a23157e698baf0b5061275b\/overview","created_at":"2026-06-13T02:33:23.000000Z","department":"Optics","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nOptical Fiber \u2013 Strategic Buyer\/Technologist\n\n**About the role**\n\n- Optical Fiber Strategic Buyer: Manage the sourcing, procurement, and supplier relationships for fiber optic cables. Key responsibilities include managing technical specifications, conducting supplier risk assessments, optimizing cost models, and ensuring supply continuity to meet project requirements.\n- Supplier Management: Identify, qualify, and manage key supplier relationships, establishing KPIs for quality, delivery, and cost performance.\n- Strategic Sourcing: Develop procurement strategies for optical components, including fiber optic cables.\n- Negotiation & Contracts: Negotiate pricing and terms & conditions.\n- Collaboration: Work with engineering, operations.\n- Fiber characterization: measure key parameters\n\n**Qualifications**\n\n- 5+ years of proven experience in strategic sourcing, ideally focusing on telecommunications, optical transport, or infrastructure.\n- Technical Knowledge: Understanding of optical fiber design, passive fiber connectivity, silicon photonics, and manufacturing processes.\n- Bachelors degree or higher in relevant technical field\n- Excellent teamwork and interpersonal\/communication skills within the company and with partners, customers, and consultants.\n- Good to have: Direct lab experience of fiber characterization and performance simulations.","categories":["Engineering"],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"5362ddee-eb46-4347-878c-a073b584d391","title":"Principal System Engineer","content":"**Job Title**\n\nPrincipal System Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**Responsibilities**\n\n- Lead a team of engineers to characterize optical transmitters, optical receivers and link performance of highly parallel opto-electronic interfaces\n- Develop and maintain optical transmission system testing bed for full characterization of optical components and modules as well as system performance measurements\n- Define and run link DOEs using uLED on ASIC transmitters, fiber bundle as transmission and PD on ASIC as receivers\n- Characterize various aspects of both existing and potential future optical components such as evaluating signal-to-noise ratio (SNR), receiver sensitivity, bit-error-rate (BER), crosstalk, power consumptions and link budget of the transmission system\n- Work with PCBA design engineers to design, fabricate and bring up test boards. Experience in schematic capture, circuit simulation and PCB design guidance\n\n**Desired Qualifications and Experience**\n\n- MS or PhD in electrical engineering or physics with 6+ years of experience\n- Expertise with optical transceiver circuits such as Trans-impedance Amplifier (TIA), laser\/led drivers and photodetectors\n- Familiarity with datacenter class optical module designs for Quad Small Form-factor Pluggable Octal Small Form Factor Pluggable (QSFP)\/(OSFP) form factor pluggable modules or emerging Near-Packaged Optics (NPO) or Co-Packaged Optics (CPO) approaches.\n- Experience with optical transceiver test methodologies\n- Familiarity with industry standards including IEEE Ethernet standards, OIF standards and MSAs\n\n**Preferred**\n\n- Ability to work cross-functionally with ASIC, packaging and optical design teams and provide clear technical inputs\n- Strong verbal and written communication skills, and ability to articulate and engage with both technical and non-technical stakeholders at all levels\n- Ability to code scripts in python for validation and data analysis\n- Working knowledge of high-speed test instruments such as VNAs, sampling and real time oscilloscopes and spectrum analyzers\n- Hands-on lab experience especially with probed\/free space coupled (using stages) optical systems","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a4ee80a3e129300850db350\/overview","created_at":"2026-07-31T07:51:50.000000Z","department":"System Test & Characterization","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nPrincipal System Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**Responsibilities**\n\n- Lead a team of engineers to characterize optical transmitters, optical receivers and link performance of highly parallel opto-electronic interfaces\n- Develop and maintain optical transmission system testing bed for full characterization of optical components and modules as well as system performance measurements\n- Define and run link DOEs using uLED on ASIC transmitters, fiber bundle as transmission and PD on ASIC as receivers\n- Characterize various aspects of both existing and potential future optical components such as evaluating signal-to-noise ratio (SNR), receiver sensitivity, bit-error-rate (BER), crosstalk, power consumptions and link budget of the transmission system\n- Work with PCBA design engineers to design, fabricate and bring up test boards. Experience in schematic capture, circuit simulation and PCB design guidance\n\n**Desired Qualifications and Experience**\n\n- MS or PhD in electrical engineering or physics with 6+ years of experience\n- Expertise with optical transceiver circuits such as Trans-impedance Amplifier (TIA), laser\/led drivers and photodetectors\n- Familiarity with datacenter class optical module designs for Quad Small Form-factor Pluggable Octal Small Form Factor Pluggable (QSFP)\/(OSFP) form factor pluggable modules or emerging Near-Packaged Optics (NPO) or Co-Packaged Optics (CPO) approaches.\n- Experience with optical transceiver test methodologies\n- Familiarity with industry standards including IEEE Ethernet standards, OIF standards and MSAs\n\n**Preferred**\n\n- Ability to work cross-functionally with ASIC, packaging and optical design teams and provide clear technical inputs\n- Strong verbal and written communication skills, and ability to articulate and engage with both technical and non-technical stakeholders at all levels\n- Ability to code scripts in python for validation and data analysis\n- Working knowledge of high-speed test instruments such as VNAs, sampling and real time oscilloscopes and spectrum analyzers\n- Hands-on lab experience especially with probed\/free space coupled (using stages) optical systems","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"0f5de66e-670f-43cc-ba91-749cf43463c0","title":"Micro LED Characterization Engineer","content":"**Job Title**\n\nMicro LED Characterization Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**Responsibilities**\n\n- Perform optical, electrical, and thermal characterization of microLED devices throughout the development lifecycle.\n- Design, develop, and maintain automated measurement systems and test scripts to improve characterization efficiency and repeatability.\n- Analyze characterization data to extract key performance metrics, including optical output power, forward voltage, emission wavelength, external quantum efficiency (EQE), and device reliability\/degradation characteristics.\n- Drive root cause analysis of device performance and reliability issues, providing data-driven recommendations to process, device, and design engineering teams.\n- Collaborate cross-functionally with process integration, epitaxy, device design, and product engineering teams to optimize device performance and manufacturing yield.\n- Develop new characterization methodologies, test procedures, and best practices to support next-generation microLED technologies.\n- Maintain, calibrate, and troubleshoot laboratory equipment to ensure measurement accuracy and reliability.\n- Document experimental procedures, results, and conclusions in clear technical reports and present findings to cross-functional teams.\n- Mentor junior engineers and technicians in characterization techniques, data analysis, and laboratory best practices.\n\n**Required Qualifications**\n\n- Bachelor's or Master's degree in Electrical Engineering, Physics, Materials Science, Optics, or a related technical field.\n- **10+ years of industry experience** in semiconductor or optoelectronic device characterization.\n- Strong understanding of electrical, optical, and thermal characterization techniques for semiconductor devices.\n- Experience with automated test systems and measurement instrumentation.\n- Strong analytical skills with proficiency in **JMP**, Python, Excel, or similar data analysis tools.\n- Experience with statistical data analysis and Design of Experiments (DOE).\n- Excellent troubleshooting, problem-solving, and root cause analysis skills.\n- Strong written and verbal communication skills, with the ability to present technical findings to multidisciplinary teams.\n- Ability to work independently in a fast-paced startup environment while collaborating effectively across engineering disciplines.\n\n**Preferred Qualifications**\n\n- Ph.D. or M.S. in Electrical Engineering, Materials Science, Physics, Optics, or a related field.\n- Direct experience with **microLED**, LED, VCSEL, laser, or other III-V semiconductor device characterization.\n- Familiarity with metrology tools such as **Scanning Electron Microscopy (SEM)**, optical microscopy, profilometry, and other optical characterization techniques.\n- Experience with reliability testing, failure analysis, and lifetime characterization.\n- Experience developing automated test software using Python, LabVIEW, or similar programming environments.\n- Knowledge of semiconductor fabrication processes and process integration.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a500915757622c985e93c23\/overview","created_at":"2026-07-31T07:53:57.000000Z","department":"FAB & Manufacturing","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nMicro LED Characterization Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**Responsibilities**\n\n- Perform optical, electrical, and thermal characterization of microLED devices throughout the development lifecycle.\n- Design, develop, and maintain automated measurement systems and test scripts to improve characterization efficiency and repeatability.\n- Analyze characterization data to extract key performance metrics, including optical output power, forward voltage, emission wavelength, external quantum efficiency (EQE), and device reliability\/degradation characteristics.\n- Drive root cause analysis of device performance and reliability issues, providing data-driven recommendations to process, device, and design engineering teams.\n- Collaborate cross-functionally with process integration, epitaxy, device design, and product engineering teams to optimize device performance and manufacturing yield.\n- Develop new characterization methodologies, test procedures, and best practices to support next-generation microLED technologies.\n- Maintain, calibrate, and troubleshoot laboratory equipment to ensure measurement accuracy and reliability.\n- Document experimental procedures, results, and conclusions in clear technical reports and present findings to cross-functional teams.\n- Mentor junior engineers and technicians in characterization techniques, data analysis, and laboratory best practices.\n\n**Required Qualifications**\n\n- Bachelor's or Master's degree in Electrical Engineering, Physics, Materials Science, Optics, or a related technical field.\n- **10+ years of industry experience** in semiconductor or optoelectronic device characterization.\n- Strong understanding of electrical, optical, and thermal characterization techniques for semiconductor devices.\n- Experience with automated test systems and measurement instrumentation.\n- Strong analytical skills with proficiency in **JMP**, Python, Excel, or similar data analysis tools.\n- Experience with statistical data analysis and Design of Experiments (DOE).\n- Excellent troubleshooting, problem-solving, and root cause analysis skills.\n- Strong written and verbal communication skills, with the ability to present technical findings to multidisciplinary teams.\n- Ability to work independently in a fast-paced startup environment while collaborating effectively across engineering disciplines.\n\n**Preferred Qualifications**\n\n- Ph.D. or M.S. in Electrical Engineering, Materials Science, Physics, Optics, or a related field.\n- Direct experience with **microLED**, LED, VCSEL, laser, or other III-V semiconductor device characterization.\n- Familiarity with metrology tools such as **Scanning Electron Microscopy (SEM)**, optical microscopy, profilometry, and other optical characterization techniques.\n- Experience with reliability testing, failure analysis, and lifetime characterization.\n- Experience developing automated test software using Python, LabVIEW, or similar programming environments.\n- Knowledge of semiconductor fabrication processes and process integration.","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"fac43526-0c0d-4378-b14c-cd31bfa798df","title":"Senior IC Packaging Engineer","content":"**Job Title**\n\nSenior IC Packaging Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\n- Lead the architecture, design, and development of advanced semiconductor packaging solutions, including 2.5D\/3D IC, System-in-Package (SiP), Flip Chip, and Wafer-Level Packaging\n- Lead development, characterization, and optimization of **TSV (Through-Silicon Via) reveal** processes, including back grind, CMP, dielectric\/barrier reveal etch, and thickness\/uniformity control across wafer thinning stacks\n- Own **C4 bumping** process flows \u2014 UBM deposition, solder bump plating or ball drop, reflow, and flux clean \u2014 for flip-chip and 3D-IC applications\n- Develop and maintain process control plans (SPC), DOEs, and yield improvement roadmaps for optical engine packaging and bumping modules\n- Partner with integration engineering to co-optimize TSV reveal with downstream hybrid bonding, micro-bump, or RDL processes\n- Troubleshoot excursions using FA data, cross-sections, and metrology (CD-SEM, profilometry, XRF, AOI) to root-cause defects such as TSV protrusion variation, via reveal non-uniformity, bump voiding, or co-planarity issues\n- Support new product\/technology introduction (NPI) from pathfinding through HVM transfer\n- Collaborate cross-functionally with design, reliability, and test teams to ensure package-level electrical and mechanical performance targets are met\n- Mentor junior engineers and contribute to internal process documentation and best-practice standards\n\n**Qualifications**\n\n- MS\/PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering or related field\n- 5+ years of hands-on experience in semiconductor packaging or wafer fab process engineering - working with major OSAT\u2019s (ASE, AMKOR, SpiL etc). An extensive personal network within key OSATs would be very advantageous\n- Direct, hands-on experience with **TSV reveal** (grinding, CMP, dielectric reveal, thickness metrology) and **C4 bumping** (UBM, electroplating or solder ball attach, reflow)\n- Strong understanding of 2.5D\/3D packaging architectures (interposers, chiplets, HBM integration, hybrid bonding is a plus)\n- Deep understanding of semiconductor device physics, packaging materials, and thermal\/mechanical analysis\n- Experience with statistical process control, DOE methodology, and yield analysis\n- Familiarity with metrology and inspection tools relevant to bumping\/TSV (CD-SEM, AFM, profilometers, X-ray, AOI\/SEM defect review)\n- Working knowledge of cleanroom fab operations and contamination control\n- Excellent cross-functional communication skills; comfortable working with equipment OEMs and multi-site teams\n\n**Preferred Qualifications**\n\n- Experience with copper pillar bumping, micro-bump, or hybrid bonding processes\n- Background in wafer thinning and temporary bonding\/debonding for advanced node packaging\n- Exposure to reliability testing (thermal cycling, electromigration, HAST) for packaged parts\n- Experience supporting HVM ramp in an OSAT or IDM environment","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a582c2e5d4f10c086f7ae47\/overview","created_at":"2026-07-31T08:02:51.000000Z","department":"Packaging","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nSenior IC Packaging Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\n- Lead the architecture, design, and development of advanced semiconductor packaging solutions, including 2.5D\/3D IC, System-in-Package (SiP), Flip Chip, and Wafer-Level Packaging\n- Lead development, characterization, and optimization of **TSV (Through-Silicon Via) reveal** processes, including back grind, CMP, dielectric\/barrier reveal etch, and thickness\/uniformity control across wafer thinning stacks\n- Own **C4 bumping** process flows \u2014 UBM deposition, solder bump plating or ball drop, reflow, and flux clean \u2014 for flip-chip and 3D-IC applications\n- Develop and maintain process control plans (SPC), DOEs, and yield improvement roadmaps for optical engine packaging and bumping modules\n- Partner with integration engineering to co-optimize TSV reveal with downstream hybrid bonding, micro-bump, or RDL processes\n- Troubleshoot excursions using FA data, cross-sections, and metrology (CD-SEM, profilometry, XRF, AOI) to root-cause defects such as TSV protrusion variation, via reveal non-uniformity, bump voiding, or co-planarity issues\n- Support new product\/technology introduction (NPI) from pathfinding through HVM transfer\n- Collaborate cross-functionally with design, reliability, and test teams to ensure package-level electrical and mechanical performance targets are met\n- Mentor junior engineers and contribute to internal process documentation and best-practice standards\n\n**Qualifications**\n\n- MS\/PhD in Materials Science, Electrical Engineering, Chemical Engineering, Mechanical Engineering or related field\n- 5+ years of hands-on experience in semiconductor packaging or wafer fab process engineering - working with major OSAT\u2019s (ASE, AMKOR, SpiL etc). An extensive personal network within key OSATs would be very advantageous\n- Direct, hands-on experience with **TSV reveal** (grinding, CMP, dielectric reveal, thickness metrology) and **C4 bumping** (UBM, electroplating or solder ball attach, reflow)\n- Strong understanding of 2.5D\/3D packaging architectures (interposers, chiplets, HBM integration, hybrid bonding is a plus)\n- Deep understanding of semiconductor device physics, packaging materials, and thermal\/mechanical analysis\n- Experience with statistical process control, DOE methodology, and yield analysis\n- Familiarity with metrology and inspection tools relevant to bumping\/TSV (CD-SEM, AFM, profilometers, X-ray, AOI\/SEM defect review)\n- Working knowledge of cleanroom fab operations and contamination control\n- Excellent cross-functional communication skills; comfortable working with equipment OEMs and multi-site teams\n\n**Preferred Qualifications**\n\n- Experience with copper pillar bumping, micro-bump, or hybrid bonding processes\n- Background in wafer thinning and temporary bonding\/debonding for advanced node packaging\n- Exposure to reliability testing (thermal cycling, electromigration, HAST) for packaged parts\n- Experience supporting HVM ramp in an OSAT or IDM environment","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"f780f0e5-b2ee-401d-bfe0-f47e2a3e6bd7","title":"Device Reliability Engineer","content":"**Job Title**\n\nDevice Reliability Engineer\n\n**About the role**\n\n- As a Device Reliability Engineer at Avicena, you will own the reliability and qualification strategy for our GaN microLED and photodetector devices powering the LightBundle\u2122 interconnect platform.\n- You will design accelerated stress tests, build lifetime and degradation models, and define the qualification criteria that ensure our devices meet demanding data-center and AI-infrastructure lifetime targets.\n\n**Responsibilities**\n\n- Reliability strategy:  \nDefine and own device-level reliability roadmaps, specification, qualification test plans (QTP), and acceptance criteria for GaN microLEDs and photodetector arrays.\n- Accelerated testing:  \nDesign and execute accelerated life tests and stress conditions (temperature, current density, humidity, thermal cycling, ESD) and build the associated test hardware\/methodology.\n- Lifetime modeling:  \nDevelop degradation and lifetime models (e.g., Arrhenius, acceleration factors, Weibull\/lognormal statistics) and project field lifetime from accelerated data.\n- Failure-mode analysis:  \nIdentify and characterize wear-out and degradation mechanisms; partner with Failure Analysis to root-cause reliability fallout and validate fixes.\n- Qualification:  \nDrive device qualification against internal and industry standards (e.g., JEDEC\/Telcordia-style methodologies) and prepare qualification reports for internal and customer use.\n- Cross-functional influence:  \nFeed reliability learnings back into device design, process, and packaging to improve robustness and margin; contribute to DfR (Design for Reliability) reviews.\n\n**Qualifications**\n\n- Education:  \nMS or PhD in Electrical Engineering, Materials Science, Physics, or a related field (or BS with equivalent industry experience).\n- Experience:  \n5\u20138+ years in device or product reliability engineering for semiconductor or optoelectronic devices.\n- Reliability methods:  \nStrong command of accelerated life testing, statistical lifetime modeling, and acceleration-factor\/failure-rate analysis.\n- Standards:  \nFamiliarity with reliability qualification standards and methodologies (JEDEC, Telcordia, or equivalent).\n- Physics of failure:  \nSolid understanding of degradation and wear-out mechanisms in semiconductor\/optoelectronic devices.\n- Analysis skills:  \nProficiency in statistical analysis and scripting (e.g., Python, MATLAB, JMP) and clear technical reporting.\n\n**Preferred Qualifications**\n\n- GaN microLEDs:  \nPrior experience with GaN-based microLED or LED\/laser reliability is strongly preferred but not required.\n- Experience qualifying high-density emitter or detector arrays.\n- Familiarity with packaging, hybrid-bonding, and heterogeneous-integration reliability.\n- Experience defining reliability requirements for data-center, optical-module, or high-reliability applications.\n- Track record building reliability test infrastructure from the ground up in a startup or early-product environment.\n\n**Compensation, Benefits & EEO**\n\n- Avicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology.\n- Actual compensation will be determined based on experience, qualifications, and location.\n- Avicena is an Equal Opportunity Employer.\n- We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic.\n- Applicants must be authorized to work in the United States.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a5fee8c538fb425997755ce\/overview","created_at":"2026-07-31T08:06:34.000000Z","department":"FAB & Manufacturing","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nDevice Reliability Engineer\n\n**About the role**\n\n- As a Device Reliability Engineer at Avicena, you will own the reliability and qualification strategy for our GaN microLED and photodetector devices powering the LightBundle\u2122 interconnect platform.\n- You will design accelerated stress tests, build lifetime and degradation models, and define the qualification criteria that ensure our devices meet demanding data-center and AI-infrastructure lifetime targets.\n\n**Responsibilities**\n\n- Reliability strategy:  \nDefine and own device-level reliability roadmaps, specification, qualification test plans (QTP), and acceptance criteria for GaN microLEDs and photodetector arrays.\n- Accelerated testing:  \nDesign and execute accelerated life tests and stress conditions (temperature, current density, humidity, thermal cycling, ESD) and build the associated test hardware\/methodology.\n- Lifetime modeling:  \nDevelop degradation and lifetime models (e.g., Arrhenius, acceleration factors, Weibull\/lognormal statistics) and project field lifetime from accelerated data.\n- Failure-mode analysis:  \nIdentify and characterize wear-out and degradation mechanisms; partner with Failure Analysis to root-cause reliability fallout and validate fixes.\n- Qualification:  \nDrive device qualification against internal and industry standards (e.g., JEDEC\/Telcordia-style methodologies) and prepare qualification reports for internal and customer use.\n- Cross-functional influence:  \nFeed reliability learnings back into device design, process, and packaging to improve robustness and margin; contribute to DfR (Design for Reliability) reviews.\n\n**Qualifications**\n\n- Education:  \nMS or PhD in Electrical Engineering, Materials Science, Physics, or a related field (or BS with equivalent industry experience).\n- Experience:  \n5\u20138+ years in device or product reliability engineering for semiconductor or optoelectronic devices.\n- Reliability methods:  \nStrong command of accelerated life testing, statistical lifetime modeling, and acceleration-factor\/failure-rate analysis.\n- Standards:  \nFamiliarity with reliability qualification standards and methodologies (JEDEC, Telcordia, or equivalent).\n- Physics of failure:  \nSolid understanding of degradation and wear-out mechanisms in semiconductor\/optoelectronic devices.\n- Analysis skills:  \nProficiency in statistical analysis and scripting (e.g., Python, MATLAB, JMP) and clear technical reporting.\n\n**Preferred Qualifications**\n\n- GaN microLEDs:  \nPrior experience with GaN-based microLED or LED\/laser reliability is strongly preferred but not required.\n- Experience qualifying high-density emitter or detector arrays.\n- Familiarity with packaging, hybrid-bonding, and heterogeneous-integration reliability.\n- Experience defining reliability requirements for data-center, optical-module, or high-reliability applications.\n- Track record building reliability test infrastructure from the ground up in a startup or early-product environment.\n\n**Compensation, Benefits & EEO**\n\n- Avicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology.\n- Actual compensation will be determined based on experience, qualifications, and location.\n- Avicena is an Equal Opportunity Employer.\n- We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic.\n- Applicants must be authorized to work in the United States.","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"0012316c-1b89-4cf6-9cab-905ff1ce536b","title":"Failure Analysis Engineer","content":"**Job Title**\n\nFailure Analysis Engineer\n\n**Job Description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\nAs a Failure Analysis Engineer at Avicena, you will be the technical detective behind our microLED and photodetector device programs \u2014 isolating, characterizing, and root-causing failures across devices, arrays, and integrated modules. Your findings will directly steer design, process, and reliability decisions for the LightBundle\u2122 platform, closing the loop between what fails in the lab and how we build it better.\n\n**Responsibilities**\n\n- Root-cause analysis:  \nLead end-to-end failure analysis of GaN microLEDs, photodetector arrays, and integrated interconnect modules, from failure isolation through physical root cause and corrective action.\n- FA techniques:  \nPlan and perform electrical, optical, and physical FA including EL\/PL imaging, SIMS, EMMI\/photoemission, OBIRCH\/thermal, curve tracing, and fault localization on single devices and dense arrays.\n- Physical analysis:  \nDirect and interpret cross-sectioning and imaging (FIB, SEM, TEM, EDX, CT\/acoustic microscopy) to identify defects, material anomalies, and interface issues.\n- Failure characterization:  \nBuild failure signatures and defect libraries; distinguish process-induced, design-induced, and stress-induced failure modes.\n- Feedback loop:  \nTranslate FA findings into actionable recommendations for device, process, packaging, and reliability teams, and verify effectiveness of corrective actions.\n- Reporting:  \nProduce clear, rigorous FA reports and present root-cause conclusions to engineering and leadership; support customer and foundry-facing analyses.\n\n**Qualifications**\n\n- Education:  \nMS or PhD in Electrical Engineering, Materials Science, Physics, or a related field (or BS with equivalent industry experience).\n- Experience:  \n5\u20138+ years of failure analysis experience in semiconductor, optoelectronic, or photonic devices.\n- Root-cause rigor:  \nDemonstrated ability to drive structured root-cause investigations (8D, fishbone, fault-tree) to definitive physical conclusions.\n- Device physics:  \nSolid understanding of semiconductor and optoelectronic device physics and common failure\/degradation mechanisms.\n- Analysis skills:  \nProficiency in data analysis and scripting (e.g., Python, MATLAB) and strong technical communication.\n\n**Preferred Qualifications**\n\n- GaN microLEDs:  \nPrior experience with GaN-based microLED or LED\/laser failure analysis is strongly preferred but not required.\n- Experience with FA on high-density emitter or detector arrays.\n- Familiarity with packaging, hybrid bonding, or heterogeneous-integration failure modes.\n- Experience supporting reliability qualification and correlating FA to stress-test results.\n- Background in optical\/photonic module or interconnect FA.\n\n**Compensation, Benefits & EEO**\n\nAvicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology. Actual compensation will be determined based on experience, qualifications, and location. Avicena is an Equal Opportunity Employer. We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic. Applicants must be authorized to work in the United States.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a5ff12e54a57a9f3b0816e1\/overview","created_at":"2026-07-31T08:07:52.000000Z","department":"FAB & Manufacturing","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nFailure Analysis Engineer\n\n**Job Description**\n\nAvicena is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\nAs a Failure Analysis Engineer at Avicena, you will be the technical detective behind our microLED and photodetector device programs \u2014 isolating, characterizing, and root-causing failures across devices, arrays, and integrated modules. Your findings will directly steer design, process, and reliability decisions for the LightBundle\u2122 platform, closing the loop between what fails in the lab and how we build it better.\n\n**Responsibilities**\n\n- Root-cause analysis:  \nLead end-to-end failure analysis of GaN microLEDs, photodetector arrays, and integrated interconnect modules, from failure isolation through physical root cause and corrective action.\n- FA techniques:  \nPlan and perform electrical, optical, and physical FA including EL\/PL imaging, SIMS, EMMI\/photoemission, OBIRCH\/thermal, curve tracing, and fault localization on single devices and dense arrays.\n- Physical analysis:  \nDirect and interpret cross-sectioning and imaging (FIB, SEM, TEM, EDX, CT\/acoustic microscopy) to identify defects, material anomalies, and interface issues.\n- Failure characterization:  \nBuild failure signatures and defect libraries; distinguish process-induced, design-induced, and stress-induced failure modes.\n- Feedback loop:  \nTranslate FA findings into actionable recommendations for device, process, packaging, and reliability teams, and verify effectiveness of corrective actions.\n- Reporting:  \nProduce clear, rigorous FA reports and present root-cause conclusions to engineering and leadership; support customer and foundry-facing analyses.\n\n**Qualifications**\n\n- Education:  \nMS or PhD in Electrical Engineering, Materials Science, Physics, or a related field (or BS with equivalent industry experience).\n- Experience:  \n5\u20138+ years of failure analysis experience in semiconductor, optoelectronic, or photonic devices.\n- Root-cause rigor:  \nDemonstrated ability to drive structured root-cause investigations (8D, fishbone, fault-tree) to definitive physical conclusions.\n- Device physics:  \nSolid understanding of semiconductor and optoelectronic device physics and common failure\/degradation mechanisms.\n- Analysis skills:  \nProficiency in data analysis and scripting (e.g., Python, MATLAB) and strong technical communication.\n\n**Preferred Qualifications**\n\n- GaN microLEDs:  \nPrior experience with GaN-based microLED or LED\/laser failure analysis is strongly preferred but not required.\n- Experience with FA on high-density emitter or detector arrays.\n- Familiarity with packaging, hybrid bonding, or heterogeneous-integration failure modes.\n- Experience supporting reliability qualification and correlating FA to stress-test results.\n- Background in optical\/photonic module or interconnect FA.\n\n**Compensation, Benefits & EEO**\n\nAvicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology. Actual compensation will be determined based on experience, qualifications, and location. Avicena is an Equal Opportunity Employer. We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic. Applicants must be authorized to work in the United States.","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"27c572ef-99d1-4db9-821b-1b6ab46728dd","title":"Device Engineer","content":"**Job Title**\n\nDevice Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\nAs a Device Engineer at Avicena, you will drive the design, fabrication, electro-optical characterization and qualification of GaN microLED devices at the heart of our LightBundle\u2122 interconnect platform. You will translate device physics into manufacturable, high-yield emitters that meet aggressive targets for efficiency, speed, and array uniformity, working across the full stack from epitaxy and process integration to on-wafer test.\n\n**Responsibilities**\n\n- **Device design & modeling:**  \nDevelop and optimize GaN-based microLED device structures, including epitaxial layer stacks, active regions, and contact schemes, using TCAD and analytical models to hit efficiency, bandwidth, current-density and reliability targets.\n- **Fabrication & integration:**  \nDefine and refine process flows in collaboration with process integration and foundry partners; own device-level design-of-experiments from wafer to characterization.\n- **Electro-optical characterization:**  \nDesign and execute L-I-V, spectral, modulation-bandwidth, and reliability-relevant measurements on single devices and large arrays; correlate results to design and process parameters.\n- **Performance improvement:**  \nDiagnose loss mechanisms (non-radiative recombination, sidewall effects, current crowding) and drive design\/process changes to improve wall-plug efficiency and high-speed performance.\n- **Cross-functional collaboration:**  \nPartner with epitaxy, process, packaging, test, and systems teams to align device performance with link-level and product requirements.\n- **Documentation:**  \nEstablish device specifications, test plans, and technical reports; contribute to IP generation and internal design reviews.\n\n**Qualifications**\n\n- **Education:**  \nMS or PhD in Electrical Engineering, Applied Physics, Materials Science, Photonics, or a related field (or BS with equivalent industry experience).\n- **Experience:**  \n5\u20138+ years of hands-on experience in semiconductor optoelectronic or LED\/laser device engineering.\n- **Device fundamentals:**  \nStrong grasp of compound-semiconductor device physics, including carrier transport, recombination, and optical emission.\n- **Characterization:**  \nProven expertise in electro-optical device characterization and data analysis (L-I-V, spectral, high-speed\/modulation measurements).\n- **Process fluency:**  \nWorking knowledge of semiconductor fabrication processes (lithography, etch, deposition, metallization) and their impact on device performance.\n- **Tools:**  \nProficiency with data analysis and scripting tools (e.g., Python, MATLAB) and TCAD or equivalent device simulation.\n\n**Preferred Qualifications**\n\n- **GaN microLEDs:**  \nPrior hands-on experience with GaN-based microLED devices is strongly preferred but not required.\n- High-speed \/ high-bandwidth LED or VCSEL device experience for optical interconnect or display applications.\n- Experience with large-area or high-density emitter arrays and array-level uniformity\/yield.\n- Familiarity with heterogeneous integration or hybrid bonding to CMOS.\n- Track record of patents or peer-reviewed publications in optoelectronic devices.\n\n**Compensation, Benefits & EEO**\n\nAvicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology. Actual compensation will be determined based on experience, qualifications, and location. Avicena is an Equal Opportunity Employer. We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic. Applicants must be authorized to work in the United States.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a5ff4353bc5dfa87c7c647a\/overview","created_at":"2026-07-31T08:09:40.000000Z","department":"FAB & Manufacturing","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nDevice Engineer\n\n**Avicena** is a privately held company developing microLED based ultra-low power high bandwidth interconnects for chip-to-chip communications. This technology will revolutionize High-Performance (HPC) and Cloud computing, as well as other industries where low power interconnects are critical like camera sensors, autonomous vehicles, and aerospace. Avicena is headquartered in Sunnyvale, California with a development center in Edinburgh, Scotland. The company was founded in 2019 by leading technologists from the optical networking industry with a track record of delivering breakthrough products. (www.avicena.tech)\n\n**About the role**\n\nAs a Device Engineer at Avicena, you will drive the design, fabrication, electro-optical characterization and qualification of GaN microLED devices at the heart of our LightBundle\u2122 interconnect platform. You will translate device physics into manufacturable, high-yield emitters that meet aggressive targets for efficiency, speed, and array uniformity, working across the full stack from epitaxy and process integration to on-wafer test.\n\n**Responsibilities**\n\n- **Device design & modeling:**  \nDevelop and optimize GaN-based microLED device structures, including epitaxial layer stacks, active regions, and contact schemes, using TCAD and analytical models to hit efficiency, bandwidth, current-density and reliability targets.\n- **Fabrication & integration:**  \nDefine and refine process flows in collaboration with process integration and foundry partners; own device-level design-of-experiments from wafer to characterization.\n- **Electro-optical characterization:**  \nDesign and execute L-I-V, spectral, modulation-bandwidth, and reliability-relevant measurements on single devices and large arrays; correlate results to design and process parameters.\n- **Performance improvement:**  \nDiagnose loss mechanisms (non-radiative recombination, sidewall effects, current crowding) and drive design\/process changes to improve wall-plug efficiency and high-speed performance.\n- **Cross-functional collaboration:**  \nPartner with epitaxy, process, packaging, test, and systems teams to align device performance with link-level and product requirements.\n- **Documentation:**  \nEstablish device specifications, test plans, and technical reports; contribute to IP generation and internal design reviews.\n\n**Qualifications**\n\n- **Education:**  \nMS or PhD in Electrical Engineering, Applied Physics, Materials Science, Photonics, or a related field (or BS with equivalent industry experience).\n- **Experience:**  \n5\u20138+ years of hands-on experience in semiconductor optoelectronic or LED\/laser device engineering.\n- **Device fundamentals:**  \nStrong grasp of compound-semiconductor device physics, including carrier transport, recombination, and optical emission.\n- **Characterization:**  \nProven expertise in electro-optical device characterization and data analysis (L-I-V, spectral, high-speed\/modulation measurements).\n- **Process fluency:**  \nWorking knowledge of semiconductor fabrication processes (lithography, etch, deposition, metallization) and their impact on device performance.\n- **Tools:**  \nProficiency with data analysis and scripting tools (e.g., Python, MATLAB) and TCAD or equivalent device simulation.\n\n**Preferred Qualifications**\n\n- **GaN microLEDs:**  \nPrior hands-on experience with GaN-based microLED devices is strongly preferred but not required.\n- High-speed \/ high-bandwidth LED or VCSEL device experience for optical interconnect or display applications.\n- Experience with large-area or high-density emitter arrays and array-level uniformity\/yield.\n- Familiarity with heterogeneous integration or hybrid bonding to CMOS.\n- Track record of patents or peer-reviewed publications in optoelectronic devices.\n\n**Compensation, Benefits & EEO**\n\nAvicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology. Actual compensation will be determined based on experience, qualifications, and location. Avicena is an Equal Opportunity Employer. We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic. Applicants must be authorized to work in the United States.","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"76112f8d-eb6b-45e8-bb9e-6d7ea76f38c8","title":"Micro Optics Fabrication Engineer","content":"**Job Title**\n\nMicro Optics Fabrication Engineer\n\n**About the role**\n\n- Experienced engineer with strong technical background in the field of micro-optics, from optical design through micro-optics assembly and manufacturing.\n- The successful candidate will be responsible for the design and development of multi-lens micro-optics components and systems.\n\n**Responsibilities**\n\n- Design and simulate the performance of functional 3D micro-optical structures such as multi-element arrays and lenses\n- Manage plans to accomplish the project on time, utilizing optical design\/analysis software and working with manufacturing partners\n- Work with micro-optic vendors to deliver prototypes\n- Develop fabrication and assembly techniques for high volume manufacturing\n- Work with opto-mechanical engineers to define mechanical tolerances and constraints at the system level\n- Process development on die bond equipment\n- Develop custom lens materials that meet reliability requirements\n\n**Qualifications**\n\n- B.S., MS, or PhD in physics, optics or materials science, or equivalent knowledge.\n- Experience in design, fabrication, and testing of lens arrays and precision molded optics\n- Deep knowledge of optical materials and material reliability testing\n- Strong communication skills, ideally combined with experience working with vendors\/suppliers\n\n**Compensation, Benefits & EEO**\n\n- Avicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology.\n- Actual compensation will be determined based on experience, qualifications, and location.\n- Avicena is an Equal Opportunity Employer.\n- We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic.\n- Applicants must be authorized to work in the United States.","url":"https:\/\/app.rippling.com\/ats\/job-requisitions\/6a62a401d9427830e44e284c\/overview","created_at":"2026-07-31T08:12:13.000000Z","department":"Optics","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nMicro Optics Fabrication Engineer\n\n**About the role**\n\n- Experienced engineer with strong technical background in the field of micro-optics, from optical design through micro-optics assembly and manufacturing.\n- The successful candidate will be responsible for the design and development of multi-lens micro-optics components and systems.\n\n**Responsibilities**\n\n- Design and simulate the performance of functional 3D micro-optical structures such as multi-element arrays and lenses\n- Manage plans to accomplish the project on time, utilizing optical design\/analysis software and working with manufacturing partners\n- Work with micro-optic vendors to deliver prototypes\n- Develop fabrication and assembly techniques for high volume manufacturing\n- Work with opto-mechanical engineers to define mechanical tolerances and constraints at the system level\n- Process development on die bond equipment\n- Develop custom lens materials that meet reliability requirements\n\n**Qualifications**\n\n- B.S., MS, or PhD in physics, optics or materials science, or equivalent knowledge.\n- Experience in design, fabrication, and testing of lens arrays and precision molded optics\n- Deep knowledge of optical materials and material reliability testing\n- Strong communication skills, ideally combined with experience working with vendors\/suppliers\n\n**Compensation, Benefits & EEO**\n\n- Avicena offers a competitive compensation package including base salary, equity, and comprehensive benefits, along with the opportunity to make foundational contributions to a category-defining technology.\n- Actual compensation will be determined based on experience, qualifications, and location.\n- Avicena is an Equal Opportunity Employer.\n- We are committed to building a diverse and inclusive team and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other protected characteristic.\n- Applicants must be authorized to work in the United States.","categories":[],"employment_type":"FULL_TIME","experience_level":null,"workplace_type":null,"salary":null},{"uuid":"fbc2628c-760b-4c76-b56d-00baa1473914","title":"Automated Test Engineer","content":"**Job Title**\n\nAutomated Test Engineer\n\n**Role Overview**\n\nWe are looking for an Automated Test Engineer to own software and hardware aspects of Avicena\u2019s custom automated testing equipment (ATE) used for wafer\u2011level ASIC and uLED testing, including test program development, probe card\/ATE debug, and data analysis.\n\n**Responsibilities**\n\n- Develop, maintain, and extend software and proprietary scripting language for custom ATE platforms  \n- test sequencer, instrument control, safety and interlocks, logging, and UI as needed  \n- Design and implement automated test flows for wafer\u2011level and die-level uLED transceiver devices, including LIV (light\u2013current\u2013voltage) characterization, photodiode responsivity, parametric tests, and reliability screens  \n- Debug test failures across the full stack: probe card electronics, load\/probe boards, cabling, instrumentation, and ATE software  \n- Work closely with probe card and hardware engineers to bring up new probe card designs, define pin\u2011maps, verify connectivity, and validate signal integrity on test stations  \n- Integrate new instruments and subsystems into the ATE (SMUs, oscilloscopes, light measurement instruments, motion stages, etc.), including driver development and calibration routines  \n- Build robust data pipelines for LIV and parametric measurements: automated collection, storage, and post\u2011processing (yield analysis, trend analysis, outlier detection, correlation with design\/process data)  \n- Create dashboards and reports for engineering and operations, including automated daily\/lot\u2011level summaries and failure analysis  \n- Support new product introduction on the tester: first silicon\/first build bring\u2011up, characterization plan execution, and transition to production flows  \n- Drive root\u2011cause analysis for test escapes, yield excursions, and systemic failures, and implement corrective actions in test code, hardware, or documentation  \n- Write and maintain technical documentation: test specifications, software design notes, ATE configuration baselines, and troubleshooting guides for operations  \n- Provide hands\u2011on support to production and lab technicians for ATE usage, including training and on\u2011call support for critical issues\n\n**Required Qualifications**\n\n- BS or MS in Electrical Engineering, Computer Engineering, or related field  \n- 1\u20134 years of experience in semiconductor test engineering, ATE development, or similar automated test roles (wafer sort, final test, or system\u2011level test)  \n- Strong proficiency in Python  \n- Demonstrated ability to debug hardware\u2011software interactions: understanding schematics, probing boards, and correlating electrical issues with software behavior  \n- Experience with basic semiconductor test methodologies: parametric testing, functional testing, and characterization; familiarity with concepts like test coverage, guardbanding, and yield  \n- Strong data analysis skills (e.g., using Python, Pandas, or similar tools) for large test datasets, including statistical analysis and visualization  \n- Working knowledge of common lab equipment (SMUs, oscilloscopes, power supplies, DAQ, signal generators) and their remote\u2011control interfaces  \n- Excellent communication and documentation skills, with a track record of writing clear test specs and debug notes\n\n**Preferred Qualifications**\n\n- Experience with wafer\u2011level probe test, including probe cards, prober integration, and chuck\/motion control  \n- Background in LED, laser diode, or optoelectronic device testing; familiarity with LIV curves, optical power measurement, and related metrics  \n- Familiarity with data infrastructure for test: SQL or time\u2011series databases and dashboarding tools  \n- Knowledge of version control (Git) and modern software development practices (code reviews, CI for test software)  \n- Exposure to reliability and qualification testing (HTOL, temperature cycling, etc.) and how these integrate with production test flows  \n- Experience working with cross\u2011functional teams (design, process, packaging, operations, and product engineering) to define and refine test requirements","url":null,"created_at":"2026-08-13T22:39:29.000000Z","department":"Testing & Automation","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nAutomated Test Engineer\n\n**Role Overview**\n\nWe are looking for an Automated Test Engineer to own software and hardware aspects of Avicena\u2019s custom automated testing equipment (ATE) used for wafer\u2011level ASIC and uLED testing, including test program development, probe card\/ATE debug, and data analysis.\n\n**Responsibilities**\n\n- Develop, maintain, and extend software and proprietary scripting language for custom ATE platforms  \n- test sequencer, instrument control, safety and interlocks, logging, and UI as needed  \n- Design and implement automated test flows for wafer\u2011level and die-level uLED transceiver devices, including LIV (light\u2013current\u2013voltage) characterization, photodiode responsivity, parametric tests, and reliability screens  \n- Debug test failures across the full stack: probe card electronics, load\/probe boards, cabling, instrumentation, and ATE software  \n- Work closely with probe card and hardware engineers to bring up new probe card designs, define pin\u2011maps, verify connectivity, and validate signal integrity on test stations  \n- Integrate new instruments and subsystems into the ATE (SMUs, oscilloscopes, light measurement instruments, motion stages, etc.), including driver development and calibration routines  \n- Build robust data pipelines for LIV and parametric measurements: automated collection, storage, and post\u2011processing (yield analysis, trend analysis, outlier detection, correlation with design\/process data)  \n- Create dashboards and reports for engineering and operations, including automated daily\/lot\u2011level summaries and failure analysis  \n- Support new product introduction on the tester: first silicon\/first build bring\u2011up, characterization plan execution, and transition to production flows  \n- Drive root\u2011cause analysis for test escapes, yield excursions, and systemic failures, and implement corrective actions in test code, hardware, or documentation  \n- Write and maintain technical documentation: test specifications, software design notes, ATE configuration baselines, and troubleshooting guides for operations  \n- Provide hands\u2011on support to production and lab technicians for ATE usage, including training and on\u2011call support for critical issues\n\n**Required Qualifications**\n\n- BS or MS in Electrical Engineering, Computer Engineering, or related field  \n- 1\u20134 years of experience in semiconductor test engineering, ATE development, or similar automated test roles (wafer sort, final test, or system\u2011level test)  \n- Strong proficiency in Python  \n- Demonstrated ability to debug hardware\u2011software interactions: understanding schematics, probing boards, and correlating electrical issues with software behavior  \n- Experience with basic semiconductor test methodologies: parametric testing, functional testing, and characterization; familiarity with concepts like test coverage, guardbanding, and yield  \n- Strong data analysis skills (e.g., using Python, Pandas, or similar tools) for large test datasets, including statistical analysis and visualization  \n- Working knowledge of common lab equipment (SMUs, oscilloscopes, power supplies, DAQ, signal generators) and their remote\u2011control interfaces  \n- Excellent communication and documentation skills, with a track record of writing clear test specs and debug notes\n\n**Preferred Qualifications**\n\n- Experience with wafer\u2011level probe test, including probe cards, prober integration, and chuck\/motion control  \n- Background in LED, laser diode, or optoelectronic device testing; familiarity with LIV curves, optical power measurement, and related metrics  \n- Familiarity with data infrastructure for test: SQL or time\u2011series databases and dashboarding tools  \n- Knowledge of version control (Git) and modern software development practices (code reviews, CI for test software)  \n- Exposure to reliability and qualification testing (HTOL, temperature cycling, etc.) and how these integrate with production test flows  \n- Experience working with cross\u2011functional teams (design, process, packaging, operations, and product engineering) to define and refine test requirements","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null},{"uuid":"230a3c35-f885-41c8-80f7-fc61b3f148b9","title":"IC Layout Designer","content":"**Job Title**\n\nIC Layout Designer\n\n**Job description**\n\nWe are looking for an experienced **IC Layout Designer** to support the physical layout of analog, mixed-signal, and high-speed integrated circuits. The candidate will work closely with circuit designers to convert schematics into high-quality layouts that meet electrical, matching, parasitic, reliability, and manufacturability requirements. The role requires strong knowledge of CMOS layout techniques, device matching, floorplanning, routing, DRC\/LVS\/debug, parasitic extraction, and layout best practices for advanced semiconductor processes.\n\n**Responsibilities**\n\n- Design and implement transistor-level IC layouts for analog, mixed-signal, and high-speed circuits.\n- Work from circuit schematics to create clean, compact, and manufacturable layouts.\n- Perform layout of devices such as MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.\n- Apply layout techniques for device matching, common-centroid structures, shielding, symmetry, dummy devices, isolation, and noise reduction.\n- Run and debug physical verification checks including **DRC, LVS, ERC, antenna checks, density checks, and reliability checks**.\n- Perform parasitic extraction and work with circuit designers to reduce unwanted resistance, capacitance, coupling, and mismatch.\n- Support layout floorplanning, block-level integration, and top-level chip assembly.\n- Follow foundry design rules and process-specific layout guidelines.\n- Work with design engineers to optimize layout for performance, area, power, yield, and reliability.\n- Prepare layout databases for tapeout and support final verification signoff.\n\n**Required Qualifications**\n\n- Associate degree, bachelor\u2019s degree, or equivalent experience in electrical engineering, microelectronics, or a related field.\n- Experience with IC layout tools such as **Cadence Virtuoso Layout Suite**.\n- Good understanding of CMOS device layout and semiconductor process layers.\n- Experience running and debugging **DRC\/LVS** using tools such as Calibre, Assura, Pegasus, or similar.\n- Ability to read and understand circuit schematics.\n- Strong attention to detail and ability to follow layout guidelines.\n- Understanding of parasitic effects, device matching, shielding, and signal integrity.\n- Good communication skills and ability to work closely with circuit designers.\n\n**Preferred Qualifications**\n\n- Experience with analog or mixed-signal blocks such as PLLs, ADCs, DACs, SerDes, bandgaps, regulators, amplifiers, oscillators, filters, or high-speed I\/O.\n- Experience with advanced CMOS nodes such as 28 nm, 16 nm, 12 nm, 7 nm, or similar.\n- Knowledge of FinFET layout rules and advanced-node restrictions.\n- Experience with top-level integration, power routing, ESD planning, and chip finishing.\n- Familiarity with electromigration, IR drop, latch-up prevention, and reliability rules.\n- Experience with layout automation, SKILL scripting, or Python is a plus.\n\n**Key Skills**\n\n- Cadence Virtuoso  \n- DRC \/ LVS \/ ERC  \n- Calibre \/ Pegasus \/ Assura  \n- Analog layout  \n- Mixed-signal layout  \n- CMOS layout  \n- Device matching  \n- Parasitic extraction  \n- Shielding and isolation  \n- Floorplanning  \n- Top-level integration  \n- Tapeout support","url":null,"created_at":"2026-08-14T17:11:27.000000Z","department":"ASIC Development Engineering","job_type":null,"location":"\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA","description":"**Job Title**\n\nIC Layout Designer\n\n**Job description**\n\nWe are looking for an experienced **IC Layout Designer** to support the physical layout of analog, mixed-signal, and high-speed integrated circuits. The candidate will work closely with circuit designers to convert schematics into high-quality layouts that meet electrical, matching, parasitic, reliability, and manufacturability requirements. The role requires strong knowledge of CMOS layout techniques, device matching, floorplanning, routing, DRC\/LVS\/debug, parasitic extraction, and layout best practices for advanced semiconductor processes.\n\n**Responsibilities**\n\n- Design and implement transistor-level IC layouts for analog, mixed-signal, and high-speed circuits.\n- Work from circuit schematics to create clean, compact, and manufacturable layouts.\n- Perform layout of devices such as MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.\n- Apply layout techniques for device matching, common-centroid structures, shielding, symmetry, dummy devices, isolation, and noise reduction.\n- Run and debug physical verification checks including **DRC, LVS, ERC, antenna checks, density checks, and reliability checks**.\n- Perform parasitic extraction and work with circuit designers to reduce unwanted resistance, capacitance, coupling, and mismatch.\n- Support layout floorplanning, block-level integration, and top-level chip assembly.\n- Follow foundry design rules and process-specific layout guidelines.\n- Work with design engineers to optimize layout for performance, area, power, yield, and reliability.\n- Prepare layout databases for tapeout and support final verification signoff.\n\n**Required Qualifications**\n\n- Associate degree, bachelor\u2019s degree, or equivalent experience in electrical engineering, microelectronics, or a related field.\n- Experience with IC layout tools such as **Cadence Virtuoso Layout Suite**.\n- Good understanding of CMOS device layout and semiconductor process layers.\n- Experience running and debugging **DRC\/LVS** using tools such as Calibre, Assura, Pegasus, or similar.\n- Ability to read and understand circuit schematics.\n- Strong attention to detail and ability to follow layout guidelines.\n- Understanding of parasitic effects, device matching, shielding, and signal integrity.\n- Good communication skills and ability to work closely with circuit designers.\n\n**Preferred Qualifications**\n\n- Experience with analog or mixed-signal blocks such as PLLs, ADCs, DACs, SerDes, bandgaps, regulators, amplifiers, oscillators, filters, or high-speed I\/O.\n- Experience with advanced CMOS nodes such as 28 nm, 16 nm, 12 nm, 7 nm, or similar.\n- Knowledge of FinFET layout rules and advanced-node restrictions.\n- Experience with top-level integration, power routing, ESD planning, and chip finishing.\n- Familiarity with electromigration, IR drop, latch-up prevention, and reliability rules.\n- Experience with layout automation, SKILL scripting, or Python is a plus.\n\n**Key Skills**\n\n- Cadence Virtuoso  \n- DRC \/ LVS \/ ERC  \n- Calibre \/ Pegasus \/ Assura  \n- Analog layout  \n- Mixed-signal layout  \n- CMOS layout  \n- Device matching  \n- Parasitic extraction  \n- Shielding and isolation  \n- Floorplanning  \n- Top-level integration  \n- Tapeout support","categories":[],"employment_type":null,"experience_level":null,"workplace_type":null,"salary":null}],"categories":["Engineering","R&D"],"locations":["\ud83c\uddfa\ud83c\uddf8 Sunnyvale, CA"],"settings":{"filterLocation":"on","filterCategory":"on","filterWorkplace":"on","filterEmployment":"on","groupByLocation":"off","groupByDepartment":"off","bestMatch":"on"}}}